Radio Frequency (RF) and Analog Mixed Signal (AMS) circuits are a major growth sector in the IC industry and a key component in the information society. Silicon bipolar technology has been the dominant RF/AMS-design technology of choice for a long time, as it can be readily combined with CMOS processing steps. Several variants of mixed bipolar/CMOS (BiCMOS) process technologies are known. For instance, the applicant provides a SiGe:C based BiCMOS technology in which a long history of breakthroughs in high performance BiCMOS for micro- and millimeter wave applications has been achieved.
The most advanced of those processes, which is known as the QuBiC process, is based on a 0.25 μm CMOS technology resulting in a good compromise between digital CMOS performance, analog RF bipolar performance and cost.
However, it can be expected that more advanced CMOS nodes will need to become available in application domains such as TV Front End applications. This is not trivial, at least from a cost perspective, as the most advanced CMOS nodes in currently in production are too expensive for e.g. the component business and RF/AMS stand-alone products. Hence, there exists a need for a low-complexity heterojunction bipolar transistor (HBT) based on advanced CMOS nodes.
In order to produce such HBTs in a CMOS process, additional process options are necessary with respect to the standard CMOS, as high RF performance requires more performance than can be achieved in a typical baseline CMOS process. In addition, low-complexity, or low-cost, bipolar add-ons to the baseline process may allow IP reuse of bipolar circuits.
It is known that it is possible to integrate a high performance bipolar transistor (fT/fMAX=130/130 GHz) in a quarter micron baseline CMOS process with a limited number of additional process steps. An example of such integration can for instance be found in U.S. Pat. No. 7,074,685.
A performance-limiting factor in a HBT in a baseline CMOS process is the intrinsic resistance of the connection between the collector contact (plug) and the buried or implanted active collector region of the HBT device. To this end, a collector sinker is implemented to provide a preferably low-ohmic electrical path from the active collector region to the collector contact. However, the state of the art collector sinker implementations suffer from two main problems.
Firstly, the collector contact resistance may be too high, which results in low DC/RF performance. For performance in the 50 GHz range, the collector resistance is important but not limiting. However, as the base and collector profiles are optimized for higher fT, collector resistance becomes increasingly critical. Therefore, the tradeoffs with respect to reducing the collector resistance while minimizing process complexity become more significant and challenging. As an example, FIG. 1 demonstrates a 1D TCAD simulation of peak-fT versus total collector resistance. The 1D simulation was performed for a doping profile that is representative for an implanted collector that contains a selectively implanted collector (SIC) used to locally increase the collector dope and obtain higher RF performance).
Apart from the collector (lateral) sheet resistance determined by the implanted or buried collector region, the connection of the implanted or buried collector towards the contact at the surface, i.e. the sinker, plays an important role in the total collector resistance of the device. The sinker resistance can be the bottleneck for the RF performance and should therefore be as low as possible. For example in low complexity HBT technologies, the collector resistances are of direct importance for the device optimization towards high performance, as is reported by Knoll et al. in “A flexible low-cost high-performance Si:Ge:C BiCMOS process with a one-mask HBT module”, Electron Devices Meeting, IEDM 2002, pages 783-786 and in “A low-cost, high-performance, high voltage complementary BiCMOS process, Electron Devices Meeting, IEDM 2006 pages 1-4.
Traditionally the sinker implant conditions are chosen to minimize the resistance for given active area. As an example, a schematic cross-section of a LC-HBT 100 is shown in FIG. 2, which comprises a substrate 10 including an active region 20 in which the collector is formed, a base region 40, emitter region 48 and a collector sinker 82 separated from the active region 20 by shallow trench insulation (STI) 30. The HBT 100 has, by way of non-limiting example, two collector sinkers 82 with collector connections 80. Emitter contact 60 and base contacts 70 are also shown. The resistance of the collector contact, which includes the sinker plug 82 and the further doped region 24, is schematically depicted as series resistance chain 110.
For the conventional approach, a dedicated sinker implant 82 is needed to make optimal use of the thermal budget of the remaining processing steps and permits a proper outdiffusion and good connection between collector region and contact 80.
An illustration of several dedicated sinker implants compared to the standard CMOS implants is given in FIG. 3. It will be clear that depending on the sinker implant conditions, the total collector resistance will change. Typically, standard CMOS implants (i.e. Nwell and Nplus) result in a sinker resistance between 100-300 Ω·μm (measured in the length direction of the device), while a dedicated sinker implant yields a resistance between 30-200 Ω·μm depending on the nature of the collector, i.e. buried or implanted. Furthermore, the contribution of the collector resistance to the feedback-loop through the collector-base capacitance is an important factor for high-frequency noise optimization in high-end BCMOS processes.
Despite the decrease in sinker resistance and increase of RF performance for optimal sinker implant conditions, one drawback of the standard approach is the need for an extra sinker mask, which adds to the cost and complexity of the manufacturing process.
Secondly, the collector sinker can have a negative impact on the device breakdown characteristics. The influence of the collector sinker dopant or impurity levels on the device breakdown is demonstrated in FIG. 4. The open-base breakdown voltage, BVCEO, strongly depends on the distance between sinker 82 and active region 20 of the device. By making the distance smaller (i.e. reducing Was shown in FIG. 4), the diffusion of the sinker results in a higher effective collector dope and lowers BVCEO.
From these results it is clear that high collector sinker dope to reduce the collector resistance, thereby improving RF performance and reducing noise as discussed previously has the disadvantage of higher active region dope due to sinker diffusion. This diffusion can be compensated by a wider shallow trench insulation 30 which places the sinker further away from the active region but this results in an increase of (total) collector resistance, larger device areas and higher collector-substrate capacitance. Therefore, high sinker doping levels for low resistive path and high RF performance are not always compatible with “high” breakdown voltage and minimum device area.